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1 ltc3733/ltc3733-1 3733f applicatio s u features typical applicatio u descriptio u 3-phase, buck controllers for amd cpus , ltc and lt are registered trademarks of linear technology corporation. burst mode, opti-loop and polyphase are registered trademarks of linear technology corporation. amd opteron is a trademark of advanced micro devices, inc. the ltc ? 3733 family are polyphase ? synchronous step- down switching regulator controllers that drive all n-channel external power mosfet stages in a phase- lockable, fixed frequency architecture. the 3-phase con- troller drives its output stages with 120 phase separation at frequencies of up to 530khz per phase to minimize the rms current dissipated by the esr of both the input and output filter capacitors. the 3-phase technique effectively triples the fundamental frequency, improving transient response while operating each phase at an optimal fre- quency for efficiency and ease of thermal design. light load efficiency is optimized by using a choice of output stage shedding or burst mode technology. a differential amplifier provides true remote sensing of both the high and low sides of the output voltage at load points. soft-start and a defeatable, timed short-circuit shutdown protect the mosfets and the load. a foldback current circuit also provides protection for the external mosfets under short-circuit or overload conditions. an all-1 vid detector turns off the regulator after 1 m s timeout. n 3-phase controller with onboard mosfet drivers n current mode control ensures current sharing n differential amplifier accurately senses v out n 5% output current matching optimizes thermal performance and size of inductors and mosfets n reduced input and output capacitance n supports active voltage positioning n vid programmable output voltage from 0.8v to 1.55v (amd opteron tm cpu) n 6-phase, 90a to 120a operation n output power good indicator with adaptive blanking n 210khz to 530khz per phase, pll, fixed frequency n synchronizable (ltc3733-1) n pwm, stage shedding or burst mode ? operation n opti-loop ? compensation minimizes c out n adjustable soft-start current ramping n short-circuit shutdown timer with defeat option n no_cpu detection n 36-lead 0.209" ssop and 38-lead (5mm 7mm) qfn n high performance notebook computers n servers, desktop computers and workstations figure 1. high current triple phase step-down converter 0.002 l1 0.8 h 22 f 35v 2 0.002 l2 0.8 h v in d1 d2 d3 0.002 c out 470 f 4v 4 v out 0.8v to 1.55v 65a v in 5v to 28v l3 0.8 h v in 3733 f01 tg1 v cc 0.1 f sw3 sw2 sw1 sw1 bg1 sense1 + sense1 boost1 boost2 boost3 tg2 sw2 bg2 pgood run pllfltr i th 0.1 f 100pf 680pf 5 vid bits 5k on/off power good indicator ss sgnd eain pgnd vid0-vid4 sense2 + sense2 tg3 sw3 bg3 sense3 + sense3 in in + pllin optional syn in + 10 f 5v + ltc3733-1
2 ltc3733/ltc3733-1 3733f absolute axi u rati gs w ww u package/order i for atio uu w topside driver voltages (boost n ) ............ 38v to C0.3v switch voltage (sw n )................................... 32v to C5v boosted driver voltage (boost n C sw n ) .... 7v to C0.3v peak output current <1ms (tg n , bg n ) ..................... 5a supply voltage (v cc ), pgood pin voltages ................................................ 7v to C0.3v pllin, run, ss, pllfltr, fcb voltages ............................. v cc to C0.3v order part number ltc3733cg t jmax = 125 c, q ja = 95 c/w consult ltc marketing for parts specified with wider operating temperature ranges. (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 vid1 run pllfltr fcb in + in diffout eain sgnd sense1 + sense1 sense2 + sense2 sense3 sense3 + ss i th vid2 vid0 pgood boost1 tg1 sw1 boost2 tg2 sw2 v cc bg1 pgnd bg2 bg3 sw3 tg3 boost3 vid4 vid3 i th voltage ................................................ 2.4v to C0.3v operating ambient temperature range ....... 0 c to 70 c junction temperature (note 2) ............................. 125 c storage temperature range ltc3733cg .......................................C65 c to 150 c ltc3733cuhf-1 ...............................C65 c to 125 c lead temperature (ltc3733cg) (soldering, 10 sec) ............................................... 300 c order part number ltc3733cuhf-1 13 14 15 16 top view 39 uhf package 38-lead (7mm 5mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 pllfltr fcb in + in diffout eain sgnd sense1 + sense1 sense2 + sense2 sense3 sw1 boost2 tg2 sw2 v cc drv cc bg1 pgnd bg2 bg3 sw3 tg3 pllin run vid1 vid0 pgood boost1 tg1 sense3 + ss i th vid2 vid3 vid4 boost3 23 22 21 20 9 10 11 12 t jmax = 125 c, q ja = 34 c/w exposed pad is sgnd (pin 39) must be soldered to pcb electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = v run = v ss = 5v unless otherwise noted. symbol parameter conditions min typ max units main control loop v regulated regulated voltage at in + (note 3); vid code = 10011, v ith = 1.2v 1.067 1.075 1.083 v l 1.064 1.075 1.086 v v sensemax maximum current sense threshold v eain = 0.5v, v ith open, 65 75 85 mv v sense1 C , v sense2 C , v sense3 C = 0.8v, 1.55v l 62 75 88 mv i match current match worst-case error at v sense(max) C5 5 % uhf part marking 37331
3 ltc3733/ltc3733-1 3733f electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = v run = v ss = 5v unless otherwise noted. symbol parameter conditions min typ max units v loadreg output voltage load regulation (note 3) measured in servo loop, d i th voltage = 1.2v to 0.7v l 0.1 0.5 % measured in servo loop, d i th voltage = 1.2v to 2v l C0.1 C0.5 % v reflnreg output voltage line regulation v cc = 4.5v to 7v 0.03 %/v g m transconductance amplifier g m i th = 1.2v, sink/source 25 m a (note 3) 2.5 3.05 3.6 mmho g mol transconductance amplifier gbw i th = 1.2v, (g m ? z l , z l = series 1k-100k w -1nf) 1.5 mhz v fcb forced continuous threshold l 0.58 0.60 0.62 v i fcb fcb bias current v fcb = 0.65v 0.2 0.7 m a v binhibit burst inhibit threshold measured at fcb pin v cc C 1.5 v cc C 0.7 v cc C 0.3 v uvr undervoltage ss reset v cc lowered until the ss pin is pulled low 3.3 3.8 4.5 v i q input dc supply current (note 4) normal mode v cc = 5v 2.5 ma shutdown v run = 0v, vid0 to vid4 open 20 100 m a v run run pin on threshold v run , ramping positive 1 1.5 1.9 v i ss soft-start charge current v ss = 1.9v C0.8 C1.5 C2.5 m a v ssarm ss pin arming threshold v ss , ramping positive until short-circuit 3.8 4.5 v latch-off is armed v sslo ss pin latch-off threshold v ss , ramping negative 3.3 v i scl ss discharge current soft-short condition v eain = 0.375v, v ss = 4.5v C5 C1.5 m a i sdlho shutdown latch disable current v eain = 0.375v, v ss = 4.5v 1.5 5 m a i sense sense pins source current sense1 + , sense1 C , sense2 + , sense2 C ,1320 m a sense3 + , sense3 C all equal 1.2v; current at each pin df max maximum duty factor in dropout 95 98.5 % tg t r, t f top gate rise time c load = 3300pf 30 90 ns top gate fall time c load = 3300pf 40 90 ns bg t r, t f bottom gate rise time c load = 3300pf 30 90 ns bottom gate fall time c load = 3300pf 20 90 ns tg/bg t 1d top gate off to bottom gate on delay all controllers, c load = 3300pf each driver 60 ns synchronous switch-on delay time bg/tg t 2d bottom gate off to top gate on delay all controllers, c load = 3300pf each driver 60 ns top switch-on delay time t on(min) minimum on-time tested with a square wave (note 5) 120 ns vid parameters vid il maximum low level input voltage 0.8 v vid ih minimum high level input voltage 2 v vid pullup vid0 to vid4 internal pull-up 150 k w resistance atten err vid0 to vid4 (note 6) l C0.25 0.25 % power good output indication v pgl pgood voltage output low i pgood = 2ma 0.1 0.3 v i pgood pgood output leakage v pgood = 5v 1 m a pgood trip thesholds v diffout with respect to set output voltage, v pgthneg v diffout ramping negative vid code = 10011 C7 C10 C14 % v pgthpos v diffout ramping positive pgood goes low after v uvdly delay 7 10 14 % t pgblnk power good blanking after vid changes outside pgood window 120 m s
4 ltc3733/ltc3733-1 3733f electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = v run = v ss = 5v unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc3733cg: t j = t a + (p d 95 c/w) ltc3733cuhf-1: t j = t a + (p d 34 c/w) note 3: the ic is tested in a feedback loop that includes the differential amplifier in a unity-gain configuration loaded with 100 m a to ground driving the vid dac into the error amplifier and servoing the resultant voltage to the midrange point for the error amplifier (v ith = 1.2v). note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 5: the minimum on-time condition corresponds to an inductor peak- to-peak ripple current of 3 40% of i max (see minimum on-time considerations in the applications information section). note 6: atten err specification is in addition to the output voltage accuracy specified at vid code 10011. note 7: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. symbol parameter conditions min typ max units oscillator and phase-locked loop f nom nominal frequency v pllfltr = 1.2v 310 350 400 khz f low lowest frequency v pllfltr = 0v 190 210 250 khz f high highest frequency v pllfltr = 2.4v 470 530 620 khz r pllth pllin input threshold ltc3733-1 only 1 v r pll in pllin input resistance ltc3733-1 only 50 k w i pll lpf phase detector output current ltc3733-1 only sinking capability f pllin < f osc 20 m a sourcing capability f pllin > f osc 20 m a r relphs controller 2-controller 1 phase 120 deg controller 3-controller 1 phase 240 deg no_cpu detection t nocpu no-cpu shutdown latency after all vid bits = 1 0.5 1 m s differential amplifier a v differential gain 0.995 1.000 1.005 v/v v os input offset voltage in + = in C = 1.2v, i out = 1ma, 0.5 5 mv input referred; gain = 1 cm common mode input voltage range 0 5 v cmrr common mode rejection ratio 0v < in + = in C < 5v, i out = 1ma, input referred 50 70 db i cl output current 10 40 ma gbp gain bandwidth product 2 mhz sr slew rate r l = 2k 5 v/ m s v o(max) maximum high output voltage i out = 1ma v cc C 1.2 v cc C 0.8 v r in input resistance measured at in + pin 80 k w
5 ltc3733/ltc3733-1 3733f typical perfor a ce characteristics uw efficiency vs i out efficiency vs v in efficiency vs frequency reference voltage vs temperature error amplifier g m vs temperature maximum i sense threshold vs temperature oscillator frequency vs temperature oscillator frequency vs v pllfltr undervoltage reset voltage vs temperature inductor current (a) 0.1 0 efficiency (%) 10 30 40 50 100 70 10 3733 g01 20 80 90 60 1 100 v fcb = open v fcb = 0v v in = 8v v out = 1.5v v fcb = 5v v in (v) 0 70 efficiency (%) 100 75 15 3733 g02 85 80 95 90 5 25 10 20 i l = 20a i l = 50a v out = 1.5v f = 210khz frequency (khz) 200 85 efficiency (%) 100 450 3733 g03 91 88 97 94 250 550 350 300 400 500 v in = 5v v in = 12v v in = 20v v out = 1.5v i load = 20a v in = 8v temperature ( c) C45 590 reference voltage (mv) 610 45 3733 g04 595 605 600 C30 90 0 C15 15 75 30 60 temperature ( c) C45 2.0 error amplifier g m (mmho) 4.0 45 3733 g05 2.5 3.5 3.0 C30 90 0 C15 15 75 30 60 temperature ( c) C45 65 maximum i sense threshold (mv) 85 45 3733 g06 70 80 75 C30 90 0 C15 15 75 30 60 v o = 1.55v v o = 0.8v temperature ( c) C45 100 frequency (khz) 600 550 500 450 400 350 300 45 3733 g07 150 250 200 C30 90 0 C15 15 75 30 60 v pllfltr = 2.4v v pllfltr = 1.2v v pllfltr = 0v v pllfltr = 5v v pllfltr (v) 0 200 frequency (khz) 550 500 450 400 350 300 3733 g08 250 1.6 2.4 0.8 0.4 1.2 2.0 temperature ( c) C45 3.0 undervoltage reset (v) 5.0 45 3733 g09 3.5 4.5 4.0 C30 90 0 C15 15 75 30 60
6 ltc3733/ltc3733-1 3733f typical perfor a ce characteristics uw short-circuit arming and latchoff vs temperature supply current vs temperature shutdown current vs temperature ss pull-up current vs temperature maximum current sense threshold vs duty factor peak current threshold vs v ith percentage of nominal output vs peak i sense (foldback) maximum duty factors vs temperature i sense pin current vs v out temperature ( c) C45 2.0 2.5 3.0 ss pin voltage (v) 5.0 45 3733 g10 3.5 4.5 4.0 C30 90 0 C15 15 75 30 60 arming latchoff temperature ( c) C45 1.0 1.4 1.8 supply current (ma) 3.0 45 3733 g11 2.2 2.6 C30 90 0 C15 15 75 30 60 temperature ( c) C45 0 5 15 shutdown current ( a) 40 45 3733 g12 25 35 10 20 30 C30 90 0 C15 15 75 30 60 temperature ( c) C45 0 0.5 1.0 ss pull-up current ( a) 2.5 45 3733 g13 1.5 2.0 C30 90 0 C15 15 75 30 60 duty factor (%) 0 0 i sense voltage (mv) 75 60 3733 g14 50 25 20 100 40 80 v ith (v) 0 C20 C10 0 i sense voltage threshold (mv) 10 30 40 50 90 70 1.6 3733 g15 20 80 60 0.8 2.4 1.2 0.4 2.0 percentage of nominal output voltage (%) 0 0 peak i sense voltage (mv) 10 30 40 50 80 70 70 3733 g16 20 60 30 100 50 10 90 60 20 40 80 temperature ( c) C45 90 92 94 maximum duty factor (%) 100 45 3733 g17 96 98 C30 90 0 C15 15 75 30 60 v pllfltr = 0v v out (v) 0 C60 C50 C40 C30 C20 C10 i sense pin current ( a) 0 1.2 3733 g18 0.2 1.6 0.6 0.4 0.8 1.0 1.4
7 ltc3733/ltc3733-1 3733f typical perfor a ce characteristics uw maximum current threshold mismatch vs temperature shed mode at 1amp, light load current burst mode at 1amp, light load current continuous mode at 1amp, light load current transient load current response: 0amp to 50amp temperature ( c) C45 0 0.5 1.0 maximum current threshold mismatch (mv) 3.0 45 3733 g19 1.5 2.5 2.0 C30 90 0 C15 15 75 30 60 v out ac, 20mv/div 4 m s/div v in = 12v v out = 1.5v v fcb = v cc frequency = 210khz 3733 g20 20 m s/div v in = 12v v out = 1.5v v fcb = open frequency = 210khz 3733 g21 4 m s/div v in = 12v v out = 1.5v v fcb = 0v frequency = 210khz 3733 g22 20 m s/div v in = 12v v out = 1.5v v fcb = 0v frequency = 210khz 3733 g23 v sw1 10v/div v sw2 10v/div v sw3 10v/div v out ac, 20mv/div v sw1 10v/div v sw2 10v/div v sw3 10v/div v out ac, 20mv/div v sw1 5v/div v sw2 5v/div v sw3 5v/div v out ac, 50mv/div i l 20a/div
8 ltc3733/ltc3733-1 3733f uu u pi fu ctio s vid0 to vid4 (pins 36, 1, 18, 19, 20/pins 35, 36, 16, 17, 18): output voltage programming input pins. a 150k internal pull-up resistor is provided on each input pin. see table 1 for details. do not apply voltage to these pins prior to the application of voltage on the v cc pin. run (pin 2/pin 37): on/off control of the ltc3733. pllfltr (pin 3/pin 1): the phase-locked loops lowpass filter is tied to this pin. alternatively, this pin can be driven with an ac or dc voltage source to vary the frequency of the internal oscillator. (do not apply voltage to this pin prior to the application of voltage on the v cc pin.) fcb (pin 4/pin 2): forced continuous control input. the voltage applied to this pin sets the operating mode of the controller. the forced continuous current mode is active when the applied voltage is less than 0.6v. burst mode operation will be active when the pin is allowed to float and a stage shedding mode will be active if the pin is tied to the v cc pin. (do not apply voltage to this pin prior to the application of voltage on the v cc pin.) in + , in C (pins 5, 6/pins 3, 4): inputs to a precision, unity- gain differential amplifier with internal precision resistors. this provides true remote sensing of both the positive and negative load terminals for precise output voltage control. diffout (pin 7/pin 5): output of the remote output voltage sensing differential amplifier. eain (pin 8/pin 6): this is the input to the error amplifier which compares the vid divided, feedback voltage to the internal 0.6v reference voltage. sgnd (pin 9/pin 7, 39): signal ground. this pin must be routed separately under the ic to the pgnd pin and then to the main ground plane. the exposed pad (qfn) must be soldered to the pcb for optimal thermal performance. sense1 + , sense2 + , sense3 + , sense1 C , sense2 C , sense3 C (pins 10 to 15/pins 8 to 13): the inputs to each differential current comparator. the i th pin voltage and built-in offsets between sense C and sense + pins, in con- junction with r sense , set the current trip threshold level. ss (pin 16/pin 14): combination of soft-start and short- circuit detection timer. a capacitor to ground at this pin sets the ramp time to full current output as well as the time delay prior to an output voltage short-circuit shutdown. a minimum value of 0.01 m f is recommended on this pin. i th (pin 17/pin 15): error amplifier output and switching regulator compensation point. all three current comparators thresholds increase with this control voltage. pgnd (pin 26/pin 24): driver power ground. this pin connects to the sources of the bottom n-channel external mosfets and the (C) terminals of c in . bg1 to bg3 (pins 27, 25, 24/pins 25, 23, 22): high current gate drives for bottom n-channel mosfets. voltage swing at these pins is from ground to v cc . drv cc (na/pin 26): high power supply to drive the external mosfet gates in qfn package. this pin needs to be closely decoupled to the ics pgnd pin. v cc (pin 28/pin 27): main supply pin. this pin supplies the controller circuit power. in the g36 package, it is also the high power supply to drive the external mosfet gates and this pin needs to be closely decoupled to the ics pgnd pin. sw1 to sw3 (pins 32, 29, 23/pins 31, 28, 21): switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in (where v in is the external mosfet supply rail). (g36/qfn)
9 ltc3733/ltc3733-1 3733f uu u pi fu ctio s (g36/qfn) tg1 to tg3 (pins 33, 30, 22/pins 32, 29, 20): high current gate drives for top n-channel mosfets. these are the outputs of floating drivers with a voltage swing equal to the boost voltage source superimposed on the switch node voltage sw. boost1 to boost3 (pins 34, 31, 21/pins 33, 30, 19): positive supply pins to the topside floating drivers. bootstrapped capacitors, charged with external schottky diodes and a boost voltage source, are connected between the boost and sw pins. voltage swing at the boost pins is from boost source voltage (typically v cc ) to this boost source voltage + v in (where v in is the external mosfet supply rail). pgood (pin 35/pin 34): this open-drain output is pulled low when the output voltage is outside the pgood toler- ance window. pgood is blanked during vid transitions for approximately 120 m s. pllin (na/pin 38): synchronization input to phase de- tector. this pin is internally terminated to sgnd with 50k w . the phase-locked loop will force the rising top gate signal of controller 1 to be synchronized with the rising edge of the pllin signal. this pin is not available in the g36 package. exposed pad (na/pin 39): signal ground. must be sol- dered to pcb.
10 ltc3733/ltc3733-1 3733f fu ctio al diagra u u w figure 2 switch logic clk2 clk1 sw shdn b 0.55v 3mv fcb top boost tg c b c in d b pgnd bot bg v cc v cc (drv cc in the ltc3733-1) v in + v out 3733 f02 drop out det run soft- start bot force bot s r q q clk3 oscillator 0.600v 0.660v 1.5 a 6v no_cpu rst shdn ss c ss 5(v fb ) 5(v fb ) slope comp + C sense + v cc 30k 45k 45k 2.4v i 1 run sgnd 0.600v internal supply v cc c cc v cc duplicate for second and third controller channels + C + C r sense l c out + + C + C + C + C in + diffout eain v fb r1 6.667k r2 variable i th c c vid0 vid1 vid2 vid3 vid4 r c in C vid transitions pgood fcb + C C + 5-bit vid decoder + v ref v cc eain 0.66v rs latch fcb 0.6v 0.54v + C i 2 sense C 30k a1 40k 40k 40k 40k ea shed C + ov 120 s blanking 1 s pllfltr 50k phase det pllin (ltc3733-1 only) f in r lp c lp 2.5 a 2.4v 100k
11 ltc3733/ltc3733-1 3733f operatio u (refer to functional diagram) main control loop the ic uses a constant frequency, current mode step- down architecture. during normal operation, each top mosfet is turned on each cycle when the oscillator sets the rs latch, and turned off when the main current comparator, i 1 , resets each rs latch. the peak inductor current at which i 1 resets the rs latch is controlled by the voltage on the i th pin, which is the output of the error amplifier ea. the eain pin receives a portion of the voltage feedback signal via the diffout pin through the internal vid dac and is compared to the internal reference voltage. when the load current increases, it causes a slight de- crease in the eain pin voltage relative to the 0.6v refer- ence, which in turn causes the i th voltage to increase until each inductors average current matches one third of the new load current (assuming all three current sensing resistors are equal). in burst mode operation and stage shedding mode, after each top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by current compara- tor i 2 , or the beginning of the next cycle. the top mosfet drivers are biased from floating boot- strap capacitor c b , which is normally recharged during each off cycle through an external schottky diode. when v in decreases to a voltage close to v out , however, the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector counts the number of oscillator cycles that the bottom mosfet remains off and periodically forces a brief on period to allow c b to recharge. the main control loop is shut down by pulling the run pin low. releasing run allows an internal 1.5 m a current source to charge soft-start capacitor c ss at the ss pin. the internal i th voltage is then clamped to the ss voltage when c ss is slowly charged up. this soft-start clamping prevents abrupt current from being drawn from the input power source. when the run pin is low, all functions are kept in a controlled state. low current operation the fcb pin is a multifunction pin: 1) an analog compara- tor input to provide regulation for a secondary winding by forcing temporary forced pwm operation and 2) a logic input to select between three modes of operation. when the fcb pin voltage is below 0.6v, the controller performs as a continuous, pwm current mode synchro- nous switching regulator. the top and bottom mosfets are alternately turned on to maintain the output voltage independent of direction of inductor current. when the fcb pin is below v cc C 1v but greater than 0.6v, the controller performs as a burst mode switching regulator. burst mode operation sets a minimum output current level before turning off the top switch and turns off the synchro- nous mosfet(s) when the inductor current goes nega- tive. this combination of requirements will, at low current, force the i th pin below a voltage threshold that will temporarily shut off both output mosfets until the output voltage drops slightly. there is a burst comparator having 60mv of hysteresis tied to the i th pin. this hysteresis results in output signals to the mosfets that turn them on for several cycles, followed by a variable sleep interval depending upon the load current. the resultant output voltage ripple is held to a very small value by having the hysteretic comparator after the error amplifier gain block. when the fcb pin is tied to the v cc pin, burst mode operation is disabled and the forced minimum inductor current requirement is removed. this provides constant frequency, discontinuous current operation over the wid- est possible output current range. at approximately 10% of maximum designed load current, the second and third output stages are shut off and the first controller alone is active in discontinuous current mode. this stage shed- ding optimizes efficiency by eliminating the gate charging losses and switching losses of the other two output stages. additional cycles will be skipped when the output load current drops below 1% of maximum designed load current in order to maintain the output voltage. this constant frequency operation is not as efficient as burst mode operation at very light loads, but does provide lower noise, constant frequency operating mode down to very light load conditions. tying the fcb pin to ground will force continuous current operation. this is the least efficient operating mode, but may be desirable in certain applications. the output can
12 ltc3733/ltc3733-1 3733f operatio u (refer to functional diagram) source or sink current in this mode. when forcing con- tinuous operation and sinking current, this current will be forced back into the main power supply, potentially boosting the input supply to dangerous voltage levels beware! frequency synchronization or setup the phase-locked loop allows the internal oscillator to be synchronized to an external source using the pllin pin. the output of the phase detector at the pllfltr pin is also the dc frequency control input of the oscillator which operates over a 210khz to 530khz range corresponding to a voltage input from 0v to 2.4v. when locked, the pll aligns the turn on of the top mosfet to the rising edge of the synchronizing signal. when no frequency information is supplied to the pllin pin, pllfltr goes low, forcing the oscillator to minimum frequency. a dc source can be applied to the pllfltr pin to externally set the desired operating frequency. in the g36 package, the pllin pin is not brought out and the pllfltr pin is for frequency setup only. differential amplifier this amplifier provides true differential output voltage sensing. sensing both v out + and v out C benefits regula- tion in high current applications and/or applications hav- ing electrical interconnection losses. this sensing also isolates the physical power ground from the physical signal ground preventing the possibility of troublesome ground loops on the pc layout and prevents voltage errors caused by board-to-board interconnects, particu- larly helpful in vrm designs. power good the pgood pin is connected to the drain of an internal mosfet. the mosfet is turned on once the output voltage has been away from its nominal value by greater than 10%. the pgood signal is blanked for approximately 120 m s during vid transitions. if a new vid transition occurs before the previous blanking time expires, the timer is reset. short-circuit detection the ss capacitor is used initially to limit the inrush current from the input power source. once the controllers have been given time, as determined by the capacitor on the ss pin, to charge up the output capacitors and provide full load current, the ss capacitor is then used as a short- circuit timeout circuit. if the output voltage falls to less than 70% of its nominal output voltage, the ss capacitor begins discharging, assuming that the output is in a severe overcurrent and/or short-circuit condition. if the condition lasts for a long enough period, as determined by the size of the ss capacitor, the controller will be shut down until the run pin voltage is recycled. this built-in latchoff can be overridden by providing >5 m a at a compliance of 4v to the ss pin. this current shortens the soft-start period but prevents net discharge of the ss capacitor during a severe overcurrent and/or short-circuit condition. foldback cur- rent limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short- circuit latchoff circuit is enabled. foldback current limit can be overridden by clamping the eain pin such that the voltage is held above the (70%)(0.6v) or 0.42v level even when the actual output voltage is low. the ss capacitor will be reset if the input voltage, (v cc ) is allowed to fall below approximately 4v. the capacitor on the pin will be discharged until the short-circuit arming latch is disarmed. the ss capacitor will attempt to cycle through a normal soft-start ramp up after the v cc supply rises above 4v. this circuit prevents power supply latchoff in the event of input power switching break-before-make situations. no_cpu detection the ltc3733 detects the presense of cpu by monitoring all vid bits. if an all-1 condition is detected, the control- ler acknowledges a no_cpu fault. if this fault condition persists for more than 1 m s, the ss pin is pulled low and the controller is shut down.
13 ltc3733/ltc3733-1 3733f applicatio s i for atio wu uu the basic application circuit is shown in figure 1 on the first page of this data sheet. external component selection is driven by the load requirement, and normally begins with the selection of an inductance value based upon the desired operating frequency, inductor current and output voltage ripple requirements. once the inductors and operating frequency have been chosen, the current sens- ing resistors can be calculated. next, the power mosfets and schottky diodes are selected. finally, c in and c out are selected according to the required voltage ripple requirements. the circuit shown in figure 1 can be configured for operation up to a mosfet supply voltage of 28v (limited by the external mosfets). operating frequency the ic uses a constant frequency architecture with the frequency determined by an internal capacitor. this ca- pacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the pllfltr pin. refer to the phase-locked loop and fre- quency synchronization and setup sections for additional information. a graph for the voltage applied to the pllfltr pin versus frequency is given in figure 3. as the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see efficiency considerations). the maximum switching frequency is approximately 530khz. inductor value calculation and output ripple current the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge and transition losses. in addition to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be consid- ered. the polyphase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. the inductor value has a direct effect on ripple current. the inductor ripple current d i l per individual section, n, decreases with higher inductance or frequency and in- creases with higher v in or v out : d i v fl v v l out out in =- ? ? ? ? 1 where f is the individual output stage operating frequency. in a polyphase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to the ripple cancellation. the details on how to calculate the net output ripple current can be found in application note 77. figure 4 shows the net ripple current seen by the output capacitors for the different phase configurations. the output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. the output ripple current is normalized against the inductor ripple current at zero duty factor. the graph can be used in place of tedious calculations. as shown in figure 4, the zero output ripple current is obtained when: v v k n where k n out in == 12 1 , , ..., figure 3. operating frequency vs v pllfltr pllfltr pin voltage (v) 550 450 350 250 150 0 0.5 1.0 1.5 2.0 2.5 operating frequency (khz) 3733 f03
14 ltc3733/ltc3733-1 3733f so the number of phases used can be selected to minimize the output ripple current and therefore the output ripple voltage at the given input and output voltages. in applica- tions having a highly varying input voltage, additional phases will produce the best results. accepting larger values of d i l allows the use of low inductances but can result in higher output voltage ripple. a reasonable starting point for setting ripple current is d i l = 0.4(i out )/n, where n is the number of channels and i out is the total load current. remember, the maximum d i l occurs at the maximum input voltage. the individual inductor ripple currents are constant determined by the inductor, input and output voltages. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and d1, d2, d3 selection at least two external power mosfets must be selected for each of the three output sections: one n-channel mosfet for the top (main) switch and one or more n-channel mosfet(s) for the bottom (synchronous) switch. the number, type and on resistance of all mosfets selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the mosfet will be used. a much smaller and much lower input capacitance mosfet should be used for the top mosfet in applications that have an output voltage that is less than 1/3 of the input voltage. in applications where v in >> v out , the top mosfets on resistance is normally less impor- tant for overall efficiency than its input capacitance at operating frequencies above 300khz. mosfet manufac- turers have designed special purpose devices that provide reasonably low on resistance with significantly reduced input capacitance for the main switch application in switch- ing regulators. the peak-to-peak mosfet gate drive levels are set by the voltage, v cc , requiring the use of logic-level threshold mosfets in most applications. pay close attention to the bv dss specification for the mosfets as well; many of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on resistance r sd(on) , input capacitance, input voltage and maximum output current. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets (figure 5). the curve is generated by forcing a constant input current applicatio s i for atio wu uu figure 4. normalized peak output current vs duty factor [i rms = 0.3(i o(p-p) ] inductor core selection once the value for l1 to l3 is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of ferrite, molypermalloy or kool m m ? cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. kool m m is a registered trademark of magnetics, inc. duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 3733 f04 6-phase 4-phase 3-phase 2-phase 1-phase i o(p-p) v o /fl
15 ltc3733/ltc3733-1 3733f into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate- to-drain capacitance. the flat portion of the curve is the result of the miller capacitance effect of the drain-to- source capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate- to-source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve specified v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufac- turers data sheet and divide by the stated v ds voltage specified. c miller is the most important selection criteria for determining the transition loss term in the top mosfet but is not directly specified on mosfet data sheets. c rss and c os are specified sometimes but definitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v synchronous switch duty cycle vv v out in in out in = = ? ? ? ? the power dissipation for the main and synchronous mosfets at maximum output current are given by: p v v i n r v i n rc vv v f p vv v i n r main out in max ds on in max dr miller cc th min th min sync in out in max ds on = ? ? ? ? + () + ()( ) + ? ? () = ? ? ? ? + () 2 2 2 1 2 11 1 d d () () () () where n is the number of output stages, d is the tempera- ture dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 w at v gs = v miller ), v in is the drain potential and the change in drain potential in the particular application. v th(min) is the data sheet specified typical gate threshold voltage specified in the power mosfet data sheet. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 12v, the high current efficiency generally improves with larger mosfets, while for v in > 12v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c rss actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short circuit when the synchronous switch is on close to 100% of the period. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but applicatio s i for atio wu uu v ds v in 3733 f05 v gs miller effect q in ab c miller = (q b ?q a )/v ds v gs v figure 5. gate charge characteristic
16 ltc3733/ltc3733-1 3733f d = 0.005/ c can be used as an approximation for low voltage mosfets. the schottky diodes, d1 to d3 shown in figure 1 conduct during the dead time between the conduction of the two large power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead time and requiring a reverse recovery period which could cost as much as several percent in efficiency. a 2a to 8a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transi- tion losses due to their larger junction capacitance. c in and c out selection input capacitance esr requirements and efficiency losses are reduced substantially in a multiphase architecture because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the rms current squared. a 3-stage, single output voltage implementation can reduce input path power loss by 90%. in continuous mode, the source current of each top n-channel mosfet is a square wave of duty cycle v out /v in . a low esr input capacitor sized for the maximum rms current must be used. the details of a close form equation can be found in application note 77. figure 6 shows the input capacitor ripple current for different phase configu- rations with the output voltage fixed and input voltage varied. the input ripple current is normalized against the dc output current. the graph can be used in place of tedious calculations. the minimum input ripple current can be achieved when the product of phase number and output voltage, n(v out ), is approximately equal to the input voltage v in or: v v k n where k n out in == 12 1 , , ..., so the phase number can be chosen to minimize the input capacitor size for the given input and output voltages. in the graph of figure 6, the local maximum input rms capacitor currents are reached when: v v k n where k n out in == 21 12 , , ..., these worst-case conditions are commonly used for de- sign because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than re- quired. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the capacitor manufacturer if there is any question. the figure 6 graph shows that the peak rms input current is reduced linearly, inversely proportional to the number n of stages used. it is important to note that the efficiency loss is proportional to the input rms current squared and therefore a 3-stage implementation results in 90% less power loss when compared to a single phase design. battery/input protection fuse resistance (if used), pc applicatio s i for atio wu uu duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.6 0.5 0.4 0.3 0.2 0.1 0 3733 f06 rms input ripple currnet dc load current 6-phase 4-phase 3-phase 2-phase 1-phase figure 6. normalized input rms ripple current vs duty factor for one to six output stages
17 ltc3733/ltc3733-1 3733f board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a polyphase system. the required amount of input capaci- tance is further reduced by the factor, n, due to the effective increase in the frequency of the current pulses. ceramic capacitors are becoming very popular for small designs but several cautions should be observed. x7r, x5r and y5v are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied. physically, if the capacitance value changes due to applied voltage change, there is a concommitant piezo effect which results in radiating sound! a load that draws varying current at an audible rate may cause an attendant varying input voltage on a ceramic capacitor, resulting in an audible signal. a secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. the voltage can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! ceramic capacitors, when properly selected and used however, can provide the lowest overall loss due to their extremely low esr. the selection of c out is driven by the required effective series resistance (esr). typically once the esr require- ment is satisfied the capacitance is adequate for filtering. the steady-state output ripple ( d v out ) is determined by: dd v i esr nfc out ripple out ?+ ? ? ? ? 1 8 where f = operating frequency of each stage, n is the number of output stages, c out = output capacitance and d i l = ripple current in each inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. the output ripple will be less than 50mv at max v in with d i l = 0.4i out(max) assuming: c out required esr < n ? r sense and c out > 1/(8nf)(r sense ) the emergence of very low esr capacitors in small, surface mount packages makes very small physical imple- mentations possible. the ability to externally compensate the switching regulator loop using the i th pin allows a much wider selection of output capacitor types. the impedance characteristics of each capacitor type is sig- nificantly different than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design. manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo and the panasonic sp surface mount types have a good (esr)(size) product. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. ceramic capacitors from avx, taiyo yuden, murata and tokin offer high capacitance value and very low esr, especially applicable for low output voltage applications. in surface mount applications, multiple capacitors may have to be paralleled to meet the esr or rms current handling requirements of the application. aluminum elec- trolytic and dry tantalum capacitors are both available in surface mount configurations. new special polymer sur- face mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several excellent choices are the avx tps, avx tpsv, the kemet t510 applicatio s i for atio wu uu
18 ltc3733/ltc3733-1 3733f series of sur face-mount tantalums or the panasonic sp series of surface mount special polymer capacitors avail- able in case heights ranging from 2mm to 4mm. other capacitor types include sanyo pos-cap, sanyo os-con, nichicon pl series and sprague 595d series. consult the manufacturer for other specific recommendations. r sense selection for output current once the frequency and inductor have been chosen, r sense1, r sense2, r sense3 are determined based on the required peak inductor current. the current comparator has a maximum threshold of 75mv/r sense and an input common mode range of sgnd to (1.1) ? v cc . the current comparator threshold sets the peak inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to-peak ripple current, d i l . allowing a margin for variations in the ic and external component values yields: rn mv i sense max = 50 the ic works well with values of r sense from 0.001 w to 0.02 w . v cc decoupling the v cc pin supples power not only the internal circuits of the controller but also the top and bottom gate drivers and therefore must be bypassed very carefully to ground with a ceramic capacitor, type x7r or x5r (depending upon the operating temperature environment) of at least 1 m f imme diately next to the ic and preferably an additional 10 m f placed very close to the ic due to the extremely high instantaneous currents involved. the total capacitance, taking into account the voltage coefficient of ceramic capacitors, should be 100 times as large as the total combined gate charge capacitance of all of the mosfets being driven. good bypassing close to the ic is necessary to supply the high transient currents required by the mosfet gate drivers while keeping the 5v supply quiet enough so as not to disturb the very small-signal high bandwidth of the current comparators. topside mosfet driver supply (c b , d b ) external bootstrap capacitors, c b , connected to the boost pins, supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged though diode d b from v cc when the sw pin is low. when one of the topside mosfets turns on, the driver places the c b voltage across the gate-source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply (v boost = v cc + v in ). the value of the boost capacitor c b needs to be 30 to 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of d b must be greater than v in(max). differential amplifier the ic has a true remote voltage sense capability. the sensing connections should be returned from the load, back to the differential amplifiers inputs through a com- mon, tightly coupled pair of pc traces. the differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback pc traces as well as ground loop disturbances. the differential amplifier out- put signal is divided down through the vid dac and is compared with the internal, precision 0.6v voltage refer- ence by the error amplifier. the amplifier has a 0 to v cc common mode input range and an output swing range of 0 to v cc C 1.2v. the output uses an npn emitter follower with 80k w feedback resis- tance. a dc resistive load to ground is required in order to sink more current. applicatio s i for atio wu uu
19 ltc3733/ltc3733-1 3733f output voltage the ic includes a digitally controlled 5-bit attenuator producing output voltages as defined in table 1. output voltages with 25mv increments are produced from 0.8v to 1.55v. each vid digital input is pulled up to a logical high with an internal 150k resistor. the input logic threshold is ap- proximately 1.2v but the input circuit can withstand an input voltage of up to 7v. on/off control the run pin provides simple on/off control for the ltc3733. driving the run pin above 1.5v permits the controller to start operating. pulling run below 0.8v puts the ltc3733 into low current shutdown (i q ? 20 m a). soft-start function the ss pin provides two functions: 1) soft-start and 2) a defeatable short-circuit latch off timer. soft-start reduces the input power sources surge currents by gradually increasing the controllers current limit (proportional to an internal buffered and clamped v ith ). the latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. a small pull-up current (>5 m a) supplied to the ss pin will prevent the overcurrent latch from operating. the following explanation describes how this function operates. an internal 1.5 m a current source charges up the c ss capacitor. as the voltage on ss increases from 0v to 2.4v, the internal current limit is increased from 0v/r sense to 75mv/r sense . the output current limit ramps up slowly, taking 1.6s/ m f to reach full current. the output current thus ramps up slowly, eliminating the starting surge current required from the input power supply. t vv a csfc iramp ss ss = m =m () 24 0 15 16 . . ./ the ss pin has an internal 6v zener clamp (see the functional diagram). applicatio s i for atio wu uu table 1. vid output voltage programming vid4 vid3 vid2 vid1 vid0 v out 0 0 0 0 0 1.550 0 0 0 0 1 1.525 0 0 0 1 0 1.500 0 0 0 1 1 1.475 0 0 1 0 0 1.450 0 0 1 0 1 1.425 0 0 1 1 0 1.400 0 0 1 1 1 1.375 0 1 0 0 0 1.350 0 1 0 0 1 1.325 0 1 0 1 0 1.300 0 1 0 1 1 1.275 0 1 1 0 0 1.250 0 1 1 0 1 1.225 0 1 1 1 0 1.200 0 1 1 1 1 1.175 1 0 0 0 0 1.150 1 0 0 0 1 1.125 1 0 0 1 0 1.100 1 0 0 1 1 1.075 1 0 1 0 0 1.050 1 0 1 0 1 1.025 1 0 1 1 0 1.000 1 0 1 1 1 0.975 1 1 0 0 0 0.950 1 1 0 0 1 0.925 1 1 0 1 0 0.900 1 1 0 1 1 0.875 1 1 1 0 0 0.850 1 1 1 0 1 0.825 1 1 1 1 0 0.800 1 1 1 1 1 shutdown
20 ltc3733/ltc3733-1 3733f fault conditions: overcurrent latchoff the ss pin also provides the ability to latch off the controllers when an overcurrent condition is detected. the ss capacitor is used initially to limit the inrush current of all three output stages. after the controllers have been given adequate time to charge up the output capacitor and provide full load current, the ss capacitor is used for a short-circuit timer. if the output voltage falls to less than 70% of its nominal value, the ss capacitor begins dis- charging on the assumption that the output is in an overcurrent condition. if the condition lasts for a long enough period, as determined by the size of the ss capacitor, the controller will be shut down until the run pin voltage is recycled. if the overload occurs during start- up, the time can be approximated by: t lo1 >> (c ss ? 0.6v)/(1.5 m a) = 4 ? 10 5 (c ss ) if the overload occurs after start-up, the voltage on the ss capacitor will continue charging and will provide addi- tional time before latching off: t lo2 >> (c ss ? 3v)/(1.5 m a) = 2 ? 10 6 (c ss ) this built-in overcurrent latchoff can be overridden by providing a pull-up resistor to the ss pin from v cc as shown in figure 7. when v cc is 5v, a 200k resistance will prevent the discharge of the ss capacitor during an overcurrent condition but also shortens the soft-start period, so a larger ss capacitor value will be required. why should you defeat overcurrent latchoff? during the prototyping stage of a design, there may be a problem with noise pick-up or poor layout causing the protection circuit to latch off the controller. defeating this feature allows troubleshooting of the circuit and pc layout. the internal foldback current limiting still remains active, thereby protecting the power supply system from failure. a deci- sion can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. the value of the soft-start capacitor c ss may need to be scaled with output current, output capacitance and load current characteristics. the minimum soft-start capaci- tance is given by: c ss > (c out )(v out ) (10 C4 ) (r sense ) the minimum recommended soft-start capacitor of c ss = 0.1 m f will be sufficient for most applications. current foldback in certain applications, it may be desirable to defeat the internal current foldback function. a negative impedance is experienced when powering a switching regulator. that is, the input current is higher at a lower v in and decreases as v in is increased. current foldback is de- signed to accommodate a normal, resistive load having increasing current draw with increasing voltage. the eain pin should be artificially held 70% above its nominal operating level of 0.6v, or 0.42v in order to prevent the ic from folding back the peak current level. a suggested circuit is shown in figure 8. applicatio s i for atio wu uu ss pin v cc r ss c ss 3733 f07 figure 7. defeating overcurrent latchoff figure 8. foldback current elimination v cc 3733 f08 calculate for 0.42v to 0.55v v cc eain q1 ltc3733
21 ltc3733/ltc3733-1 3733f the emitter of q1 will hold up the eain pin to a voltage in the absence of v out that will prevent the internal sensing circuitry from reducing the peak output current. remov- ing the function in this manner eliminates the external mosfets protective feature under short-circuit condi- tions. this technique will also prevent the short-circuit latchoff function from turning off the part during a short- circuit event and the output current will only be limited to n ? 75mv/r sense . undervoltage reset in the event that the input power source to the ic (v cc ) drops below 4v, the ss capacitor will be discharged to ground and the controller will be shut down. when v cc rises above 4v, the ss capacitor will be allowed to re- charge and initiate another soft-start turn-on attempt. this may be useful in applications that switch between two supplies that are not diode connected, but note that this cannot make up for the resultant interruption of the regulated output. phase-locked loop and frequency synchronization (ltc3733-1) the ic has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. this allows the top mosfet of output stage 1s turn-on to be locked to the rising edge of an external source. the frequency range of the voltage controlled oscillator is 50% around the center frequency f o . a voltage applied to the pllfltr pin of 1.2v corresponds to a frequency of approximately 350khz. the nominal operating frequency range of the ic is 210khz to 530khz. the phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector will not lock the internal oscillator to harmonics of the input frequency. the pll hold-in range, d f h , is equal to the capture range, d f c : d f h = d f c = 0.5 f o the output of the phase detector is a complementary pair of current sources charging or discharging the external filter components on the pllfltr pin. a simplified block diagram is shown in figure 9. if the external frequency (f pllin ) is greater than the oscil- lator frequency, f osc , current is sourced continuously, pulling up the pllfltr pin. when the external frequency is less than f osc , current is sunk continuously, pulling down the pllfltr pin. if the external and internal fre- quencies are the same, but exhibit a phase difference, the current sources turn on for an amount of time correspond- ing to the phase difference. thus, the voltage on the pllfltr pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point, the phase comparator output is open and the filter capacitor c lp holds the voltage. the ic pllin pin must be driven from a low impedance source such as a logic gate located close to the pin. when using multiple ics for a phase-locked system, the pllfltr pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the masters frequency. a voltage of 1.7v or below applied to the master oscillators pllfltr pin is recommended in order to meet this requirement. the resultant operating frequency will be approximately 500khz for 1.7v. applicatio s i for atio wu uu external osc 2.4v r lp 10k c lp osc digital phase/ frequency detector phase detector/ oscillator pllin (ltc3733-1 only) 3733 f09 pllfltr 50k figure 9. phase-locked loop block diagram
22 ltc3733/ltc3733-1 3733f applicatio s i for atio wu uu the loop filter components (c lp , r lp ) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp =10k and c lp ranges from 0.01 m f to 0.1 m f. minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ic is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge of the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t v vf on min out in () < () if the duty cycle falls below what can be accommodated by the minimum on-time, the ic will begin to skip every other cycle, resulting in half-frequency operation. the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. the minimum on-time for the ic is generally about 120ns. however, as the peak sense voltage decreases the mini- mum on-time gradually increases. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. if an application can operate close to the minimum on- time limit, an inductor must be chosen that is low enough in value to provide sufficient ripple amplitude to meet the minimum on-time requirement. as a general rule, keep the inductor ripple current equal to or greater than 30% of i out(max) at v in(max) . efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load ? esr, where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out , generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time, v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior, but also provides a dc coupled and ac filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response . assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external com- ponents shown in the figure 1 circuit will provide an adequate starting point for most applications.
23 ltc3733/ltc3733-1 3733f the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.2 to 5 times their suggested values) to maximize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 80% of full load current having a rise time of <2 m s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the initial output voltage step, resulting from the step change in output current, may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual over- all supply performance. a second, more severe transient is caused by switching in loads with large (>1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if c load is greater than 2% of c out , the switch rise time should be controlled so that the load rise time is limited to approximately 1000 ? r sense ? c load . thus a 250 m f capacitor and a 2m w r sense resistor would require a 500 m s rise time, limiting the charging current to about 1a. design example (using three phases) as a design example, assume v in = 12v(nominal), v in = 20v(max), v out = 1.3v, i max = 45a and f = 400khz. the inductance value is chosen first based upon a 30% ripple current assumption. the highest value of ripple current in each output stage occurs at the maximum input voltage. l v fi v v v khz a v v h out out in = d () - ? ? ? ? = ()()() - ? ? ? ? 3 m 1 13 400 30 15 1 13 20 068 . % . . using l = 0.6 m h, a commonly available value results in 34% ripple current. the worst-case output ripple for the three stages operating in parallel will be less than 11% of the peak output current. r sense1, r sense2 and r sense3 can be calculated by using a conservative maximum sense current threshold of 65mv and taking into account half of the ripple current: r mv a sense = + ? ? ? ? =w 65 15 1 34 2 0 0037 % . use a commonly available 0.003 w sense resistor. next verify the minimum on-time is not violated. the minimum on-time occurs at maximum v cc : t v vf v v khz ns on min out in max () = () = () = () . 13 20 400 162 applicatio s i for atio wu uu
24 ltc3733/ltc3733-1 3733f the output voltage will be set by the vid code according to table 1. the power dissipation on the topside mosfet can be estimated. using a fairchild fds6688 for example, r ds(on) = 7m w , c miller = 15nc/15v = 1000pf. at maximum input voltage with t(estimated) = 50 c: p v v cc a pf vv v khz w main ? () + () - () [] + () ()() ? ? ? ? w ()( ) + ? ? ? ? () = 18 20 15 1 0 005 50 25 0 007 20 45 23 2 1000 1 518 1 18 400 2 2 2 2 . . . . . . w the worst-case power dissipation by the synchronous mosfet under normal operating conditions at elevated ambient temperature and estimated 50 c junction tem- perature rise is: p vv v aw sync = - ()( ) w () = 20 1 3 20 15 1 25 0 007 1 84 2 . .. . a short circuit to ground will result in a folded back current of: i mv m ns v h a sc ? + () w + () m ? ? ? ? = 25 23 1 2 150 20 06 75 . . with a typical value of r ds(on) and d = (0.005/ c)(50 c) = 0.25. the resulting power dissipated in the bottom mosfet is: p sync = (7.5a) 2 (1.25)(0.007 w ) ? 0.5w which is less than one third of the normal, full load conditions. incidentally, since the load no longer dissi- pates any power, total system power is decreased by over 90%. therefore, the system actually cools significantly during a shorted condition! pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the applicatio s i for atio wu uu ic. these items are also illustrated graphically in the layout diagram of figure 10. check the following in the pc layout: 1) are the signal and power ground paths isolated? keep the sgnd at one end of a printed circuit path thus preventing mosfet currents from traveling under the ic. the ic signal ground pin should be used to hook up all control circuitry on one side of the ic, routing the copper through sgnd, under the ic covering the shadow of the package, connect- ing to the pgnd pin and then continuing on to the (C) plates of c in and c out . the v cc decoupling capacitor should be placed immediately adjacent to the ic between the v cc pin and pgnd. a 1 m f ceramic capacitor of the x7r or x5r type is small enough to fit very close to the ic to minimize the ill effects of the large current pulses drawn to drive the bottom mosfets. an additional 5 m f to 10uf of ceramic, tantalum or other very low esr capacitance is recommended in or- der to keep the internal ic supply quiet. the power ground returns to the sources of the bottom n-channel mosfets, anodes of the schottky diodes and (C) plates of c in , which should have as short lead lengths as possible. 2) does the ic in + pin connect to the (+) plates of c out ? a 30pf to 300pf feedforward capacitor between the diffout and eain pins should be placed as close as possible to the ic. 3) are the sense C and sense + printed circuit traces for each channel routed together with minimum pc trace spacing? the filter capacitors between sense + and sense C for each channel should be as close as possible to the pins of the ic. connect the sense C and sense + pins to the pads of the sense resistor as illustrated in figure 11. 4) do the (+) plates of c in connect to the drains of the topside mosfets as closely as possible? this capacitor provides the pulsed current to the mosfets. 5) keep the switching nodes, switch, boost and tg away from sensitive small-signal nodes. ideally the switch, boost and tg printed circuit traces should be routed away and separated from the ic and the quiet side of the ic. 6) the filter capacitors between the i th and sgnd pins should be as close as possible to the pins of the ic.
25 ltc3733/ltc3733-1 3733f applicatio s i for atio wu uu figure 10. branch current waveforms + r in v in v out c in bold lines indicate high, switching current lines. keep lines to a mininmum length + c out d3 d2 sw2 d1 l1 sw1 r sense1 l2 r sense2 l3 sw3 r sense3 3732 f10 r l figure 11. kelvin sensing r sense sense + ltc3733 1000pf inductor output capacitor sense resistor 3733 f11 sense
26 ltc3733/ltc3733-1 3733f figure 10 illustrates all branch currents in a three-phase switching regulator. it becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. high elec- tric and magnetic fields will radiate from these loops just as radio stations transmit signals. the output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. the left half of the circuit gives rise to the noise generated by a switching regulator. the ground terminations of the synchronous mosfets and schottky diodes should return to the bottom plate(s) of the input capacitor(s) with a short isolated pc trace since very high switched currents are present. a separate isolated path from the bottom plate(s) of the input and output capacitor(s) should be used to tie in the ic power ground pin (pgnd). this technique keeps inherent signals generated by high current pulses taking alternate current paths that have finite impedances during the total period of the switching regulator. external opti-loop compensation allows over- compensation for pc layouts which are not optimized but this is not the recommended design procedure. simplified visual explanation of how a 3-phase controller reduces both input and output rms ripple current the effect of multiphase power supply design significantly reduces the amount of ripple current in both the input and output capacitors. the rms input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). the output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. figure 12 graphically illustrates the principle. applicatio s i for atio wu uu figure 12. single and polyphase current waveforms sw v single phase triple phase i cin i cout sw1 v sw2 v sw3 v i l1 i l2 i l3 i cin i cout 3732 f12
27 ltc3733/ltc3733-1 3733f applicatio s i for atio wu uu the worst-case input rms ripple current for a single stage design peaks at twice the value of the output voltage. the worst-case input rms ripple current for a two stage design results in peaks at 1/4 and 3/4 of the input voltage, and the worst-case input rms ripple current for a three stage design results in peaks at 1/6, 1/2, and 5/6 of the input voltage. the peaks, however, are at ever decreasing levels with the addition of more phases. a higher effective duty factor results because the duty factors add as long as the currents in each stage are balanced. refer to an19 for a detailed description of how to calculate rms current for the single stage switching regulator. figure 6 illustrates the rms input current drawn from the input capacitance versus the duty cycle as determined by the ration of input and output voltage. the peak input rms current level of the single phase system is reduced by 2/3 in a 3-phase solution due to the current splitting between the three stages. the output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the v out /l discharge currents term from the stages that has their bottom mosfets on subtract current from the (v cc C v out )/l charging current resulting from the stage which has its top mosfet on. the output ripple current for a 3-phase design is: i p-p = ()( ) () > v fl dc v v out in out 13 3 the ripple frequency is also increased by three, further reducing the required output capacitance when v cc < 3v out as illustrated in figure 4. efficiency calculation to estimate efficiency, the dc loss terms include the input and output capacitor esr, each mosfet r ds(on) , induc- tor resistance r l , the sense resistance r sense and the forward drop of the schottky rectifier at the operating output current and temperature. typical values for the design example given previously in this data sheet are: main mosfet r ds(on) = 7m w (9m w at 90 c) sync mosfet r ds(on) = 7m w (9m w at 90 c) c inesr = 20m w c outesr = 3m w r l = 2.5m w r sense = 3m w v schottky = 0.8v at 15a (0.7v at 90 c) v out = 1.3v v in = 12v i max = 0.8v at 15a (0.7v at 90 c) d = 0.01% c n = 3 f = 400khz the main mosfet is on for the duty factor v out /v in and the synchronous mosfet is on for the rest of the period or simply (1 C v out /v in ). assuming the ripple current is small, the ac loss in the inductor can be made small if a good quality inductor is chosen. the average current, i out is used to simplify the calaculations. the equation below is not exact but should provide a good technique for the comparison of selected components and give a result that is within 10% to 20% of the final application.
28 ltc3733/ltc3733-1 3733f applicatio s i for atio wu uu the temperature of the mosfets die temperature may require interative calculations if one is not familiar typical performance. a maximum operating junction tempera- ture of 90 to 100 c for the mosfets is recommended for high reliability applications. common output path dc loss: pn i n r r c loss compath max l sense outesr ? ? ? ? ? + () + 2 this totals 3.375w + c outesr loss. total of all three main mosfets dc loss: pn v v i n r c loss main out in max ds on inesr = ? ? ? ? ? ? ? ? + () + 2 1 d () this totals 0.83w + c inesr loss. total of all three synchronous mosfets dc loss: pn v v i n r sync out in max ds on = ? ? ? ? ? ? ? ? + () 11 2 () d this totals 5.4w. total of all three main mosfets ac loss: pv a pf vv v khz w main in ?w + ? ? ? ? = 3 45 23 2 1000 1 518 1 18 400 6 3 2 () ()() ()( ) . . (). this totals 1w at v in = 8v, 2.25w at v in = 12v and 6.25w at v in = 20v. total of all three synchronous mosfets ac loss: () () ()( ) ( ) 361545 q v v fnc v v e g in dsspec in dsspec = this totals 0.08w at v in = 8v, 0.12w at v in = 12v and 0.19w at v in = 20v. the bottom mosfet does not experience the miller capacitance dissipation issue that the main switch does because the bottom switch turns on when its drain is close to ground. the schottky rectifier loss assuming 50ns nonoverlap time: 2 ? 3(0.7v)(15a)(50ns)(4e5) this totals 1.26w. the total output power is (1.3v)(45a) = 58.5w and the total input power is approximately 60w so the % loss of each component is as follows: main switch ac loss (v in = 12v) 2.25w 3.75% main switch dc loss 0.83w 1.4% synchronous switch ac loss 0.19w 0.3% synchronous switch dc loss 5.4w 9% power path loss 3.375w 5.6% the numbers above represent the values at v in = 12v. it can be seen from this simple example that two things can be done to improve efficiency: 1) use two mosfets on the synchronous side and 2) use a smaller mosfet for the main switch with smaller c miller to better balance the ac loss with the dc loss. a smaller, less expensive mosfet can actually perform better in the task of the main switch.
29 ltc3733/ltc3733-1 3733f typical applicatio u 65a power supply for amd opteron processors v cc 10k 51k vid1 in on/off 30pf 1000pf s1 + s1 s2 + 5v s2 s3 s3 + vid1 run pllfltr fcb in + in diffout ltc3733 eain sgnd sense1 + sense1 sense2 + sense2 sense3 sense3 + ss i th vid2 vid0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 pgood boost1 tg1 sw1 boost2 tg2 sw2 v cc bg1 pgnd bg2 bg3 sw3 tg3 boost3 vid4 vid3 100pf v cc 5v v in m1 m2 d1 s1 + s1 l1 0.002 220pf 0.1 f 1k 100pf 22.1k 71.5k 1000pf 1 f vid0 in vid4 in vid3 in 3733 ta01 v in : 7v to 21v v out : 0.8v to 1.55v, 65a switching frequency: 300khz pgood 47k 1 1000pf vid2 in 10 f 0.1 f v cc 0.1 f 0.1 f v cc v cc v in m3 m4 d2 s2 + s2 l2 0.002 v in m5 m6 d3 s3 + s3 l3 0.002 10 f 6.3v 3 c out v in 7v to 21v v out + 10 f 35v 5 c in 68 f 25v + c in : sanyo os-con 25sp68m c out : 330 f/2.5v 10 sanyo poscap 2r5tpe330m9 d1 to d3: mbrs340t3 l1 to l3: 0.68 h sumida cep125-0r6 m1, m3, m5: hat2168h 1 or irf7811w 2 or si7860dp 1 m2, m4, m6: hat2165h 2 or irf7822 2 or si7892dp 2 block diagram6-phase ltc3731/ltc3733-1 supply 3-phase ltc3731 clkout diffout clk 60 v in v out 0.8v to 1.55v 90a to 120a 3-phase ltc3733-1 pllin 3733 ta02 in in + i th eain
30 ltc3733/ltc3733-1 3733f u package descriptio g package 36-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) g36 ssop 0802 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.50 ?13.10* (.492 ?.516) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 2.0 (.079) 0.05 (.002) 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12
31 ltc3733/ltc3733-1 3733f u package descriptio uhf package 38-lead plastic qfn (7mm 5mm) (reference ltc dwg # 05-08-1701) 5.00 0.10 (2 sides) note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 0.40 0.10 37 1 2 38 bottom view?xposed pad 5.15 0.10 (2 sides) 7.00 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 0303 0.50 bsc 0.200 ref 0.200 ref 0.00 ?0.05 recommended solder pad layout 3.15 0.10 (2 sides) 0.18 0.18 0.23 0.435 0.00 ?0.05 0.75 0.05 0.70 0.05 0.50 bsc 5.20 0.05 (2 sides) 3.20 0.05 (2 sides) 4.10 0.05 (2 sides) 5.50 0.05 (2 sides) 6.10 0.05 (2 sides) 7.50 0.05 (2 sides) 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
32 ltc3733/ltc3733-1 3733f lt/tp 1203 1k ? printed in usa ? linear technology corporation 2003 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com part number description comments ltc1628 2-phase, dual output synchronous step-down reduces c in and c out , power good output signal, synchronizable, dc/dc controllers 3.5v v in 36v, i out up to 20a, 0.8v v out 5v ltc1629/ 20a to 200a polyphase synchronous controllers expandable from 2-phase to 12-phase, uses all ltc1629-pg surface mount components, no heat sink, v in up to 36v ltc1702 no r sense tm 2-phase dual synchronous step-down 550khz, no sense resistor controller ltc1703 no r sense 2-phase dual synchronous step-down mobile pentium ? iii processors, 550khz, controller with 5-bit mobile vid control v in 7v ltc1708-pg 2-phase, dual synchronous controller with mobile vid 3.5v v in 36v, vid sets v out1 , pgood lt ? 1709/ high efficiency, 2-phase synchronous step-down 1.3v v out 3.5v, current mode ensures lt1709-8 switching regulators with 5-bit vid accurate current sharing, 3.5v v in 36v ltc1735 high efficiency synchronous step-down output fault protection, 16-pin ssop switching regulator ltc1736 high efficiency synchronous controller with 5-bit mobile output fault protection, 24-pin ssop, vid control 3.5v v in 36v ltc1778 no r sense current mode synchronous step-down up to 97% efficiency, 4v v in 36v, 0.8v v out (0.9)(v in ), controller i out up to 20a ltc1929/ 2-phase synchronous controllers up to 42a, uses all surface mount components, ltc1929-pg no heat sinks, 3.5v v in 36v ltc3708 dual, 2-phase, no r sense synchronous buck with up/down output voltage tracking, track up to 8 supplies, output tracking fast transient response ltc3711 no r sense current mode synchronous step-down up to 97% efficiency, ideal for pentium iii processors, controller with digital 5-bit interface 0.925v v out 2v, 4v v in 36v, i out up to 20a ltc3719 2-phase, 5-bit vid current mode, high efficiency amd hammer-k8 processors, wide v in range: 4v to 36v operation synchronous step-down controller ltc3729 20a to 200a, 550khz polyphase synchronous controller expandable from 2-phase to 12-phase, uses all surface mount components, v in up to 36v ltc3731 3-phase, 600khz synchronous buck expandable from 3-phase to 12-phase, uses all surface mount switching regulator controller components, v in up to 36v ltc3732 3-phase, 5-bit vid, 600khz synchronous buck vrm9.0 and vrm9.1 (vid = 1.1v to 1.85v) switching regulator controller no r sense is a trademark of linear technology corporation. pentium is a registered trademark of intel corporation. related parts

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